Technical Field
Embodiments disclosed herein are related to computing systems, and more particularly, to efficiently indicating branch target addresses.
Description of the Relevant Art
With each generation, semiconductor chips provide more functionality and performance. For example, the semiconductor chips include superscalar processing of instructions, overlapping pipeline stages, out-of-order and speculative execution of instructions, simultaneous multi-threading, and so forth. To support both superscalar and speculative execution, the semiconductor chip fetches multiple instructions simultaneously and predicts the next fetch address to begin fetching instructions.
Control flow instructions perform a determination of which path to take in an instruction stream. Control dependencies caused by conditional control flow instructions serialize instructions at conditional forks and joins along the control flow graph of the source code. Speculative execution of instructions is used to perform parallel execution of instructions despite control dependencies in the source code. The next fetch address to fetch instructions may differ from a next sequential address as occurs with a typical fetch. The sequential address may differ from the current fetch address by a given offset. The next fetch address that is a non-sequential address may differ from the current fetch address by a displacement larger than the given offset.
In various examples, the next fetch address may be specified as a relative displacement within the control flow instruction. An immediate field within the control flow instruction may store the relative displacement. After the control flow instruction is fetched and the opcode is decoded, the relative displacement may be added with the current fetch address or the next sequential address. The result of the addition is the target address. The semiconductor chip includes a next fetch predictor for selecting between at least the next sequential address and the target address. The selected address is used to fetch instructions to process following the control flow instruction.
To reduce the amount of processing performed for a control flow instruction with a relative displacement, predecoding and generation of the target address may occur prior to the control flow instruction being stored in the instruction cache. After fetching, the target address may be used earlier by next fetch prediction logic since generation is already done. However, the semiconductor chip may utilize virtual-to-physical mappings for addresses. Memory accesses within a virtual address space visible to software applications are translated to a physical address space corresponding to the actual physical memory available to the computing system. A condition known as aliasing may occur when two or more virtual addresses map to a same physical address. A first virtual address may be generated during predecoding and stored in the instruction cache. The first virtual address may point to a first physical address. A read cache hit in the instruction cache may occur for a second virtual address different from the first virtual address, wherein the second virtual address also points to the first physical address. Data corruption may now occur followed by erroneous operation by the software application.
In view of the above, efficient methods and mechanisms for efficiently indicating branch target addresses are desired.